OSHWA is concerned with all types of hardware designs. This includes designs which target Field Programmable Gate Arrays (FPGAs), typically expressed using Hardware Description Languages (HDLs) like VHDL, Verilog and SystemVerilog.

While finding a place on the Web to host your HDL code is straight-forward, reusability of these designs has in some cases suffered from a number of issues. These include absence of ancillary files, lack of high-quality testbenches and documentation, awkward licensing choices and publishing of all-rights-reserved code automatically generated by the tools provided by FPGA vendors.

OSHWA has teamed up with the FOSSi Foundation to provide a set of guidelines to help designers share HDL code efficiently. For those of you who are starting with FPGA design, the document provides an introduction and a short section on nomenclature before moving on to the best practices proper. These guidelines may become the basis for an HDL certification program in the future. For the time being, we hope they are useful to all FPGA designers and we invite you to post questions and comments in the forums to help us make them better.