Guidelines for sharing FPGA designs published

OSHWA is concerned with all types of hardware designs. This includes designs which target Field Programmable Gate Arrays (FPGAs), typically expressed using Hardware Description Languages (HDLs) like VHDL, Verilog and SystemVerilog.

While finding a place on the Web to host your HDL code is straight-forward, reusability of these designs has in some cases suffered from a number of issues. These include absence of ancillary files, lack of high-quality testbenches and documentation, awkward licensing choices and publishing of all-rights-reserved code automatically generated by the tools provided by FPGA vendors.

OSHWA has teamed up with the FOSSi Foundation to provide a set of guidelines to help designers share HDL code efficiently. For those of you who are starting with FPGA design, the document provides an introduction and a short section on nomenclature before moving on to the best practices proper. These guidelines may become the basis for an HDL certification program in the future. For the time being, we hope they are useful to all FPGA designers and we invite you to post questions and comments in the forums to help us make them better.

Open Source Hardware (and Gateware) for 5G

OSHWA recently sent a response to the 5G Challenge Notice of Inquiry published by the National Telecommunications and Information Administration (NTIA) in the US. The Notice of Inquiry focuses on the development of an open-source software stack for 5G wireless communication. In our response we highlighted the role that Field-Programmable Gate Arrays (FPGAs) can play in the path from the radio receiver to the 5G software stack and conversely from the software stack to the radio transmitter. FPGAs can cope with very high data rates, for which pure software solutions can be suboptimal.

It is therefore important that FPGA designs are made part of the challenge, and also that these designs be open-source for the same reasons that it makes sense to open-source the software stack. FPGA design is typically done using Hardware Description Languages (HDLs). HDL code is fed to synthesis, place & route and bitstream generation tools. The bitstream file then configures the FPGA, so its logic gates and flip-flops implement the circuit specified in the design. HDL code is sometimes called “gateware” (a reference to the logic gates it targets) to distinguish it from software.

If researchers and developers are going to collaborate on common open-source gateware and software, they would ideally do so using an open hardware platform. This would democratize access, enlarging the talent pool which can contribute to the effort. It would also protect the development against vendor lock-in and save time and effort on porting to different imperfectly-compatible platforms.

Finally, this could be an opportunity to improve the Free and Open Source Software tools for gateware design. There are thriving communities of open-source software-defined radio and FPGA tool developers, and we believe including them in this challenge and having hardware and gateware in the picture will result in a better 5G for everyone.